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Dot Matrix Controller Board
The Dot Matrix Controller Board provides the logic and voltage for the Dot Matrix Display/Driver.
This board interfaces the Dot Matrix Display /Driverwith WPC .
Logic
The CPU writes a bit mapped image into the RAM on the Dot Matrix Controller Board and can
control which page area is displayed. The bit mapped image corresponds to the points on the Dot
Mat rix Display/Driver. The RAM can store 16 fuJI display images at one time. There are three
74LS175 page registers that give the CPU access to the RAM .The high and low page registers are
accesse ddirectly by the CPU. These page registers point to one of 16RAMareas each, for the CPU
to read and write from. The third page register po ints to the RAMarea which is act ively displayed.
There is one additional register that allows the CPU to know whichrow of the dis play the contro ller
is cu rrently updating . The Do t Matrix Cont roller automatica llymultiplexes and refres hes the
screen according to the data in the RAM. The system clock controls access to the RAM so there are
no wait states.
Power
The voltages necessary (except the +5V which is supplied by the Powe rDriver Board) for the Dot
Matrix Display/D river Board are provided by the Dot Matrix Controller. The voltages are
regulated DC +62V(power), +12V(logic),~125(power) and, ~1 l3V(log ic;~125Vplus ~113V ::::+12V).
Decod es (Ul, U2)
VI,
a 74HCL138,selects whether to the access to the RAM(port )or , Registers (control). U2 also a
75HCT138, selects whic hregisters to access .
RAM Circu it (U24, U25, U26, U27, U29,
V3 1,
U32. U33, U35)
U33 and U35 are both 74LS175 chips and, control which page the system accesses. U31 and U32 ,also
74LS175 chips, control which page is displayed. U25, U26 and, U27 all 74LS157 chips, multiplex the
access to the RAMbetween the controller boa rds and the system according to the E clock.
E! low
=
system has access.
E! high
=
cont roller has access.
U29, a 74HC165 ,is a para llel to serial shifter .
Control Logic (U5, U6, UI0,
un,
U12, U13, U14, U15, U21)
U1O,
un
and, U12 are all 74HC161 chips, U12 generates the start of a row scan. U13, U14 and U15
are all 74HC193 chips. They generate addresses for the sequence of bits on the serial port to the
display/driver board. U22 a 74HC374,U21 a 74HC688 and U5 a 74HC74 generate the interrupt on a
row being displayed which is determined by the system. U23 a 74HC27 and U6 a 74HC04 func tion
together as a Row 1 Detect circuit.
Dot Mat rix Di splay lDri ver Board
The Dot Matrix Display/Driver Boar d is a 128 column and 32 row gas discha rge display unit. The
column drive rs have output latches so that the co lumn data for the fol lowing row can be entered
while the present is being displayed. The boar d requires three positive and two negative vo ltages,
a clock signal and, serial data sim ilar to the type used to drive a CRT or other scann ing type
displays.
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